1. Field of the Invention
The present invention relates to a method and apparatus for improving electromigration reliability and resistance of damascene and dual-damascene vias using a controlled diffusivity barrier. In particular, the present invention relates to a method and apparatus for providing an imperfect barrier to allow for some leakage of atoms therethrough in order to reduce the possibility of void formation due to electromigration in semiconductor devices.
2. Description of the Related Art
As semiconductor device geometries continue to scale down below 0.5 .mu.m, and approach 0.18 .mu.m and smaller minimum feature sizes, the metal interconnect lines that carry current between devices on a chip begin to dominate the overall circuit speed. In order to enhance interconnect speed and reliability, the semiconductor industry has been moving away from blanket deposition and etch of aluminum (Al)-based metallizations towards damascene and dual-damascene interconnect structures with copper (Cu)-based metallizations. Cu is a lower resistivity metal than Al, which results in a lower RC-interconnect delay. Cu has also been shown to have superior electromigration performance over Al. However, Cu interconnects are more difficult to process, primarily because: a) it is more difficult to etch, and b) it acts as a deep level trap in silicon (Si)-based devices.
While Al does have its benefits, including low melting temperature (660.degree. C.) and its low eutectic temperature with Si (577.degree. C.), Al interconnects begin to form hillocks at relatively low processing temperatures (i.e., above 300.degree. C.), as well as the electromigration problem discussed above. Attempts to alleviate these problems involve the addition of alloy materials to Al or the formation of multilayer-Al conductor structures. The addition of other metals to form Al alloys, however, typically results in the degradation of one or more of the Al characteristics, such as degraded resistivity, corrosion resistance, etchability, and/or bondability. For these reasons, copper-based damascene and dual-damascene interconnects are now being utilized instead of the standard Al-based interconnects for semiconductor devices.
FIG. 1A shows a conventional interconnect structure, with Al-alloy in a SiO.sub.2 dielectric, with tungsten (W) plugs as vias. The Al-alloy stack is shown by regions 10, 20, and the tungsten plugs are shown by regions 30, 40. The Al-alloy stack 10, 20 is formed in a SiO.sub.2 layer 50. As a result, connectivity down to the substrate 60 can be provided, but with the problems as discussed above.
One such problem with Al-alloy interconnects, or any other type of interconnects in small-sized geometries, is electromigration. Electromigration is the motion of ions of a conductor (such as Al or Cu) in response to the passage of current through it. These ions are moved downstream by the force of the electron wind. A positive divergence of the ionic flux leads to an accumulation of vacancies, or voids, in the metal. Such voids may grow to a large enough size so as to cause an open-circuit failure of the conductor line.
The problem of electromigration is discussed in detail in Silicon Processing for the VLSI Era, Vol. 2, by S. Wolf et al., pages 264-267. In particular, S. Wolf notes that the failure rate due to electromigration is increased when the current density in the conductor line is increased. Due to smaller-sized semiconductor devices being formed (geometries less than 0.5 .mu.m), high current densities in interconnect lines are a reality that must be addressed.
Techniques for increasing the resistance of an interconnect process to electromigration failure for standard Al-based interconnects include: a) adding Cu (0.5-4%) to the Al film; b) adding titanium (Ti) (0.1-0.5%) to the Al film; c) using a layered Al film structure, with a highly electromigration resistant metal (e.g., Ti, W, or Mo) as the central layer of a trilayer film; d) planarizing the intermetal dielectric, to eliminate thinning of the conductor lines as they cross steps, e) selectively depositing a layer of CVD tungsten (W) over the Al lines, f) avoiding the use of Al:Si when fabricating narrow, multilevel-metal structures, and g) replacing the Al metallization with a more electromigration-resistance metal, such as W or Mo. None of these techniques have been completely successful.
As discussed above, the semiconductor industry is moving away from Al and towards Cu as an interconnect metal. The preferred way to process Cu interconnects is to: a) etch a trench or via into a dielectric material, b) deposit the interconnect metallization to fill the trench or via, and then c) polish the metal back to remove any metal from the field (surface of the wafer). The resulting metal-filled trenches and vias form the electrical interconnect.
Forming an interconnect structure by filling a trench or via with metal is known as a damascene process. If a trench and underlying via are filled simultaneously, it is known as a dual-damascene process.
FIG. 1B shows a dual-damascene interconnect structure, with a trench 110 and a via 120 formed in a low-k dielectric layer 130. After the forming of the trench 110 and the via 120, metal (e.g., copper) is deposited into these regions, and then a polishing step is performed, as explained above.
A refractory metal, such as Ti, TiN, Ta, TaN, or WN, is typically deposited prior to the deposition of Al or Cu-based metallizations in damascene processing. This barrier layer prevents Al or Cu diffusion into the surrounding dielectric, and improves the quality of the metal/dielectric interface. The refractory metal acts as a diffusion barrier, which prevents the intermixing of materials from the metal layer and the surrounding dielectric. A diffusion barrier used in integrated circuit fabrication is typically a thin film inserted between an overlying metal and an underlying metal, or between two metals in a multilevel metal system. The optimal characteristics of a diffusion barrier are discussed in detail in Silicon Processing for the VLSI Era, Vol. 2, by S. Wolf et al., pages 121-131, mentioned above. By having a diffusion barrier that is formed by a metal, such as a refractory metal, the copper interconnect metal is prevented from diffusing into the adjacent dielectric material, where it may work its way down to the transistors on the wafer, thereby causing damage to the transistors.
In order to obtain adequate step coverage in high aspect ratio trenches and vias, several deposition techniques have been developed to give very directional deposition. These deposition techniques include using ionized metal plasma (IMP), having a high target-to-substrate distance, and using a hollow cathode magnetron. Typically, these deposition techniques are optimized to give the maximum step coverage on all surfaces inside the damascene structure.